1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device for simultaneously forming a dual metal damascene structure and a metal-insulator-metal capacitor.
2. Description of Related Art
With the increase of the integration of the semiconductor device, in the deep sub-micron process, the size of the device is reduced and the space for forming the capacitor is decreased as well. The capacitance of a capacitor depends on the surface area of the upper electrode and the lower electrode. Currently, the way to increase the capacitance of the capacitor with the decrease of the size of the capacitor includes selecting a dielectric layer having relatively high capacitance and increasing the surface area of the lower electrode of the capacitor.
When the material having relatively high dielectric constant is used in the process of manufacturing the capacitor to overcome the problem mentioned above, the material used to form the upper and the lower electrodes is changed as well to highlight the performance of the capacitor. Notably, because of the low interfacial reaction of the metal-insulator-metal (MIM) structure capable of improving the performance of the capacitor, the MIM structure is widely commercially used in industry.
Additionally, as the line width being decreased to deep sub-micron, the copper is used to form inner connects. However, it is not easy to etch copper. Hence, metal damascene process is used to replace the conventional method for manufacturing the copper wire structure. Recently, several manufacturing process about forming the MIM capacitor and the metal damascene structure are disclosed, such as those shown in U.S. Pat. No. 6,025,226 and U.S. Pat. No. 6,649,464.
FIG. 1A through FIG. 1B are cross-sectional views showing the conventional method (disclosed in U.S. Pat. No. 6,025,226) for manufacturing a semiconductor device having a capacitor and a metal damascene structure.
As shown in FIG. 1A, a substrate 105 having a metal layer 110 and a metal layer 115 formed thereon is provided. A dielectric layer 107 is formed on the substrate 105. An opening 120 and a via hole 130 are formed in the dielectric layer 107. A conformal insulator layer 122 is formed over the substrate 105.
As shown in FIG. 1B, the insulator layer 122 and the dielectric layer 107 are patterned to form a trench 132 over the via hole 130. A metal layer 124 is formed to fill the via hole 130 and the trench 132 to form a dual damascene structure and a metal layer 126 is formed to fill the opening 120. The metal layer 126, the insulator layer 122 and the metal layer 110 together form an MIM capacitor.
In the process mention above, since the insulator layer 122 is also formed in the via hole 130, the size of the via hole 130 is decreased. Therefore, the aspect ratio of the via hole 130 is increased. When the aspect ration of the via hole 130 is increased, it is difficult to fill out the via hole 130 with metal and it is easy to form carven in the via hole 130 during filling the via hole 130 with metal. Therefore, the leakage of the metal wires will happen easily and the performance of the device is decreased.
FIG. 2A through FIG. 2C are cross-sectional views showing the conventional method (disclosed in U.S. Pat. No. 6,649,464) for manufacturing a semiconductor device having a capacitor and a metal damascene structure.
As shown in FIG. 2A, a substrate 200 having a barrier layer 204, a metal layer 214, a barrier layer 202 and a metal layer 212 formed thereon is provided. A sealing layer 210 is formed over the substrate 200. A dielectric layer 220 having an opening 230 exposing the metal layer 212 is formed over the substrate 200. A dielectric layer 222 is formed over the substrate 200. Further, a barrier layer 232 and a metal layer 242 is formed in the opening 230. A sealing layer 240 is formed over the substrate 200. The metal layer 212, the dielectric layer 222 and the metal layer 242 together form an MIM capacitor.
As shown in FIG. 2B, an via hole 260 is formed in the dielectric layer 220 and the sealing layer to expose the metal layer 214. A barrier 234 and a metal layer 244 are formed in the via hole 260. A sealing layer 270 is formed over the substrate 200.
As shown in FIG. 2C, after a dielectric layer 280 is formed over the substrate 200, a trench 274 and an opening 272 are formed in the dielectric layer 280. A barrier layer 254 and a metal layer 264 are formed in the trench 274 and a barrier layer 242 and a metal layer 262 are formed in the opening 272. The metal layer 264 and the metal layer 234 together form a dual metal damascene structure.
In the process mentioned above, the dual metal damascene is formed after the MIM capacitor is formed. Because it is necessary to perform several times of metal deposition process, chemical mechanical polishing process and photolithography process, the cost of the manufacturing process is increased.